| 发明名称 | Three dimensional dual-port bit cell and method of using same | ||
| 摘要 | A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. | ||
| 申请公布号 | US9171849(B2) | 申请公布日期 | 2015.10.27 |
| 申请号 | US201314032222 | 申请日期 | 2013.09.20 |
| 申请人 | Taiwan Semiconductor Manufacturing Co., Ltd. | 发明人 | Chan Wei Min;Wu Wei-Cheng;Chen Yen-Huei |
| 分类号 | G11C5/06;H01L27/11;G11C11/412;G11C11/413;G11C8/16;H01L27/06;G11C5/02;G11C8/08 | 主分类号 | G11C5/06 |
| 代理机构 | Duane Morris LLP | 代理人 | Duane Morris LLP |
| 主权项 | 1. A three dimensional dual-port bit cell comprising: a first portion disposed on a first tier, wherein said first portion comprises a plurality of port elements; and a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein said second portion comprises a latch, wherein said first tier further comprises a first control circuit and a first write driver of a first port. | ||
| 地址 | Hsin-Chu TW | ||