Electrostatic discharge shunting circuit

摘要

An integrated electrostatic discharge (ESD) shunting circuit includes a III-V semiconductor layer, and a first drain-less high electron mobility transistor (HEMT) or a metal-semiconductor FET (MESFET) transistor having a first gate and at least a second drain-less HEMT or MESFET having a second gate formed in the substrate. The HEMTs or MESFETs include a donor layer on the semiconductor layer, no drains, and a source including an ohmic contact layer on the donor layer.

主权项

1. An electrostatic discharge (ESD) protection circuit with trigger, comprising:
an ESD trigger circuit for coupling between a first terminal to be protected and another terminal; and an ESD shunting circuit including a high electron mobility transistors (HEMT) or a metal-semiconductor FET (MESFET) transistor including a substrate comprising a III-V semiconductor layer having a single doped layer on said semiconductor layer that includes a raised portion and a recessed portion; at least one gate contacting said recessed portion of said single doped layer and at least one second terminal directly contacting said recessed portion of said single doped layer for providing a Drain-like function, and a source on said raised portion of said single doped layer, wherein said second terminal is only directly connected to said terminal to be protected; wherein said gate is coupled to receive a triggering signal from said ESD trigger circuit and said second terminal is configured for coupling to said terminal to be protected, and wherein said ESD shunting circuit provides a conducting channel between said second terminal and said source during an ESD event at said terminal to be protected.