Programmable logic device with improved security

摘要

Techniques of the present invention impede power consumption measurements of an encryption engine on a logic device by running the encryption engine with an independent clock. This clock produces a signal that is decoupled from and asynchronous to clock signals feeding other circuits on the device. The clock feeding the encryption engine is not accessible externally to the device. Circuits may be employed to intentionally slow down or add jitter to one or more of the clock signals.

主权项

1. A logic device comprising:
at least one logic block driven by a first clock signal; and a decryption core configured to process encrypted input data, the decryption core driven by a second clock signal, the second clock signal being one or both of decoupled from the first clock signal and asynchronous to the first clock signal; wherein: the decryption core generates plaintext output data to configure the at least one logic block.