| 发明名称 | Interpolation circuit and receiving circuit | ||
| 摘要 | An interpolation circuit includes: a plurality of holding circuits configured to each hold a corresponding input data input chronologically; and a generating circuit configured to generate interpolation data by giving weights, based on an interpolation code, to input data that are chronologically adjacent to each other and are held by the plurality of holding circuits and combining the weighted data together. | ||
| 申请公布号 | US9165166(B2) | 申请公布日期 | 2015.10.20 |
| 申请号 | US201414179133 | 申请日期 | 2014.02.12 |
| 申请人 | FUJITSU LIMITED | 发明人 | Hamada Takayuki;Tsukamoto Sanroku |
| 分类号 | G06G7/28;G06G7/30 | 主分类号 | G06G7/28 |
| 代理机构 | Arent Fox LLP | 代理人 | Arent Fox LLP |
| 主权项 | 1. An interpolation circuit comprising: a plurality of holding circuits each configured to hold, using respective capacitors, corresponding input data that are inputted chronologically; and a generating circuit configured to generate interpolation data by performing a weighting operation on at least two pieces of the input data, which are chronologically adjacent to each other and are outputted by the plurality of holding circuits, based on an interpolation code that is used for generating interpolation data from the at least two pieces of the input data and combining weighted data of the at least two pieces of the input data. | ||
| 地址 | Kawasaki JP | ||