| 主权项 |
1. A semiconductor device comprising:
a processor; a memory; a plurality of tags; a plurality of ways each of which can store a plurality of data of consecutive addresses of the memory in which the tag value stored in the each tag is taken as the reference address; and a cache controller, wherein each of the ways is provided with an address change direction flag that indicates either the direction in which the address is incremented or decremented with respect to the last two accesses to the way, wherein when a first access and a second access are accesses that are performed in succession to consecutive addresses from the processor to the memory, and when the second access is the access through a first way, the cache controller is configured to allow prefetching of data, which is indicated by the tag value continuous in the direction that the address change direction flag indicates with respect to the tag value corresponding to the first way, to a second way having the address change direction flag that matches the address change direction corresponding to the first way, and having the tag value continuous in the direction opposite to the direction that the address change direction flag indicates with respect to the tag value corresponding to the first way. |
