Stackable molded microelectronic packages with area array unit connectors

摘要

A microelectronic package having a substrate, a microelectronic element, e.g., a chip, and terminals can have conductive elements electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant can overlie the first surface of the substrate and at least a portion of a face of the microelectronic element remote from the substrate, and may have a major surface above the microelectronic element. A plurality of package contacts can overlie a face of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses, substantially rigid posts, can be electrically interconnected with terminals of the substrate, such as through the conductive elements. The package contacts can have top surfaces at least partially exposed at the major surface of the encapsulant.

主权项

1. A microelectronic package comprising:
a first substrate having a first surface, a second surface remote from the first surface, a plurality of first substrate contacts exposed at the first surface and a plurality of terminals electrically interconnected with the first substrate contacts and exposed at the second surface; a second substrate remote from the first substrate, the second substrate having a first surface, a second surface remote from the first surface and a plurality of second substrate contacts exposed at the second surface of the second substrate and a plurality of pads exposed at the second surface of the second substrate; a microelectronic element disposed between the first surface of the first substrate and the first surface of the second substrate, the microelectronic element having a first face, a second face remote from the first face, and element contacts exposed at the first face, one of the first or second faces being juxtaposed with the first surface of the first substrate; a plurality of wire bonds projecting above the first surface of the first substrate and extending between the first substrate contacts and the second substrate contacts, at least some of the wire bonds being electrically insulated from one another and adapted to simultaneously carry different electric potentials; a continuous encapsulant overlying the first surface of the first substrate, the wire bonds, and at least a portion of the second surface of the second substrate, the continuous encapsulant defining a major surface; and a plurality of package contacts exposed at the major surface of the encapsulant and overlying the second surface of the second substrate and the first or second face of the microelectronic element, the package contacts projecting above a height of the second substrate contacts, the package contacts being electrically interconnected with the element contacts of the microelectronic element through at least the wire bonds, openings extending downwardly from the major surface of the encapsulant, the package contacts including solid metal posts of copper or gold extending within the openings, the posts plated onto the pads, wherein at least top surfaces of the package contacts are at least partially exposed at the major surface of the continuous encapsulant, and the package contacts are configured to simultaneously carry respective different electric potentials.