发明名称 APPARATUS AND METHOD FOR SOURCE SYNCHRONOUS TESTING OF SIGNAL COVERTERS
摘要 An automatic tester, comprising a first signal converter, a first signal path, and a second signal path. The first signal converter is operable to convert, using a conversion clock signal, a signal from a digital signal domain to an analog signal domain to acquire an analog stimulus signal. The first signal path is operable to forward the analog stimulus signal from the first signal converter to a second signal converter operable to convert the analog stimulus signal back from the analog signal domain to the digital signal domain. The second signal path is operable to forward one of the conversion clock signal and a signal derived thereof from the first signal converter to the second signal converter. A difference between a propagation delay of an analog stimulus signal in response to a clock cycle of the conversion clock signal via the first signal path and a propagation delay of the conversion clock signal of the clock cycle via the second signal path is within a predetermined tolerance range.
申请公布号 US2015288373(A1) 申请公布日期 2015.10.08
申请号 US201013640287 申请日期 2010.04.09
申请人 Laquai Bernd 发明人 Laquai Bernd
分类号 H03M1/06;H03M1/10 主分类号 H03M1/06
代理机构 代理人
主权项 1. Automatic tester (40), comprising: a first signal converter (41) for converting, using a conversion clock signal (CLK), a signal from a digital signal domain to an analog signal domain to obtain an analog stimulus signal (STIM); a first signal path (42) for forwarding the analog stimulus signal (STIM) from the first signal converter (41) to a second signal converter (43), which is adapted to convert the analog stimulus signal (STIM) back from the analog signal domain to the digital signal domain; and a second signal path (44) for forwarding the conversion clock signal (CLK) or a signal derived thereof (CLK′) from the first signal converter (41) to the second signal converter (43), such that a difference (Δt) between a propagation delay of an analog stimulus signal (STIM) in response to a clock cycle of the conversion clock signal (CLK) via the first signal path (42) and a propagation delay of the conversion clock signal of said clock cycle via the second signal path (44) is within a predetermined tolerance range.
地址 Stuttgart DE