发明名称 Configurable storage elements
摘要 Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably act either as non-transparent (i.e., clocked) storage elements or transparent configurable storage elements. In some embodiments, the configurable storage element in the routing fabric performs both routing and storage operations by a parallel distributed path that includes a clocked storage element and a bypass connection. In some embodiments, the configurable storage element perform both routing and storage operations by a pair of master-slave latches but without a bypass connection. The routing fabric in some embodiments supports the borrowing of time from one clock cycle to another clock cycle by using the configurable storage element that can be configure to perform both routing and storage operations in different clock cycles. In some embodiments, the routing fabric provide a low power configurable storage element that includes multiple storage elements that operates at different phases of a slower running clock.
申请公布号 US9154134(B2) 申请公布日期 2015.10.06
申请号 US201414281775 申请日期 2014.05.19
申请人 Altera Corporation 发明人 Voogel Martin;Teig Steven;Chanack Thomas S.;Caldwell Andrew;Ko Jung;Chandler Trevis
分类号 H03K19/177;H01L25/00;H03K19/0185 主分类号 H03K19/177
代理机构 代理人
主权项 1. An integrated circuit (“IC”) comprising: a plurality of configurable logic circuits for configurably performing a plurality of logic operations based on configuration data; a configurable routing fabric for configurably routing signals among the configurable logic circuits, the configurable routing fabric comprising a particular wiring path connecting an output of a source circuit to inputs of a destination circuit; a first configuration retrieval path for retrieving configuration data for the source circuit; and a second configuration retrieval path for retrieving configuration data for the destination circuit, wherein the first configuration retrieval path is slower than the second configuration retrieval path.
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