发明名称 Shared interrupt control method and system for a digital signal processor
摘要 Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.
申请公布号 US2007088938(A1) 申请公布日期 2007.04.19
申请号 US20050253906 申请日期 2005.10.18
申请人 CODRESCU LUCIAN;ANDERSON WILLIAM C 发明人 CODRESCU LUCIAN;ANDERSON WILLIAM C.
分类号 G06F7/38 主分类号 G06F7/38
代理机构 代理人
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