| 摘要 |
PURPOSE:To reduce jitter by forming a required variable frequency clock by a direct digital synthesizer(DDS), accessing a digital waveform memory and executing D/A conversion and high frequency component removal or the like. CONSTITUTION:A digital waveform is read out from the first waveform memory 2 with the output of an adder 1, which adds an output to be operated synchro nously with the master clock of the DDS and a frequency value, as an address and passed through a first D/A converter 3 and first LPF 4 and a binary signal is outputted from a comparator 6 which compares the read waveform with the level '0' of a required threshold value. This output of the DDS is defined as the address and divided with a designated frequency dividing ratio. Then, an address generator 7 generates the address of a frequency with a double span to the frequency of the master clock, and the second waveform memory 8 is accessed. Afterwards, the read digital waveform is outputted through a second D/A converter 9 and second LPF 10. Thus, the memory 8 is read our from the same point of each waveform memory 8 over all frequency ranges, and the waveform is obtained while suppressing the jitter at a minimum. |
