发明名称 MULTILAYER CIRCUIT BOARD ANALYSIS SYSTEM, MULTILAYER CIRCUIT BOARD ANALYSIS METHOD, AND MULTILAYER CIRCUIT BOARD ANALYZER
摘要 PROBLEM TO BE SOLVED: To provide an electrical property analysis system of a multilayer circuit substrate capable of obtaining the voltage, current and impedance of the multilayer circuit substrate even when the mesh size in modeling does not meet the size of a via. SOLUTION: Since this substrate analysis device can analyze a wiring pattern using correction model data for canceling the difference between an electrical parameter when assuming that current may have flowed from the surrounding plane toward the via and an electrical parameter in a mesh model, the wiring pattern including the via can be properly analyzed even when using a mesh with a larger size in relation to the diameter of the via. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009075792(A) 申请公布日期 2009.04.09
申请号 JP20070243203 申请日期 2007.09.20
申请人 NEC CORP 发明人 KUSUMOTO MANABU;KOBAYASHI NAOKI
分类号 G06F17/50;H05K3/00 主分类号 G06F17/50
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