Interrupt distribution scheme

摘要

In one embodiment, an interrupt controller may implement an interrupt distribution scheme for distributing interrupts among multiple processors. The scheme may take into account various processor state in determining which processor should receive a given interrupt. For example, the processor state may include whether or not the processor is in a sleep state, whether or not interrupts are enabled, whether or not the processor has responded to previous interrupts, etc. The interrupt controller may implement timeout mechanisms to detect that an interrupt is being delayed (e.g. after being offered to a processor). The interrupt may be re-evaluated at the expiration of a timeout, and potentially offered to another processor. The interrupt controller may be configured to automatically, and atomically, mask an interrupt in response to delivering an interrupt vector for the interrupt to a responding processor.

主权项

1. An interrupt controller comprising:
circuitry coupled to receive interrupts from one or more devices in a system; and an interrupt router coupled to the circuitry and configured to select a processor from a plurality of processors in the system for a first received interrupt, wherein one or more previous interrupts were received by the interrupt router prior to receiving the first received interrupt, and wherein the interrupt router is configured to cause an interrupt to be signalled to the selected processor, wherein the interrupt router is configured to monitor a status of the plurality of processors and to select the selected processor from a group of most eligible processors responsive to the status, and wherein the interrupt router is configured to exclude one or more processors of the plurality of processors from the group of most eligible processors responsive to the one or more processors having been non-responsive to previous interrupts, wherein the interrupt router is configured to determine that the one or more processors are non-responsive during the previous interrupts responsive to offering the previous interrupts to the one or more processors and detecting a lack of acceptance of the interrupt by the one or more processors within a specified time interval.