| 摘要 |
Provided is an amplifier circuit with cross wiring of direct-current signals and microwave signals, which includes: two branch sub-circuits being mirrors with each other and a third capacitor The sub-circuit includes a direct-current feeding circuit and a microwave signal circuit. The direct-current feeding circuit further comprising: a transistor core drain power-up port (Vds) of a heterojunction field effect transistor (FET), a first micro-strip inductor, a first capacitor, a pair of third inductors, a pair of branched second inductors. The microwave signal circuit further comprising: A pair of third inductors, a pair of first capacitors, a pair of second capacitors, a pair of ground inductors, a pair of fourth inductors, a serially connected fifth inductor. |
| 主权项 |
1. An A amplifier circuit with cross wiring of direct-current signals and microwave signals, comprising two branch mirror sub-circuits (201, 202) and a third capacitor (2101) connected in parallel to an output end, wherein the branch mirror sub-circuits comprises a direct-current feeding circuit and a microwave signal circuit, the direct-current feeding circuit is mainly formed of a transistor core drain power-up port (Vds) of a heterojunction field effect transistor (FET), a first capacitor (281), a first micro-strip inductor (241), a pair of second inductors (231, 232), and a pair of third inductors (211, 212), the transistor core drain power-up port (Vds) of the heterojunction FET is connected to the first micro-strip inductor (241) in series after passing through the first capacitor (281) connected in parallel, is respectively connected to one of a pair of third inductors (211, 212) in series by a pair of branched second inductors (231, 232), and is respectively connected to a transistor core drain port of the heterojunction FET, the microwave signal circuit is mainly formed of a pair of third inductors (211, 212), a pair of second capacitors (221, 222), a pair of first capacitors (251. 252), a pair of ground inductors (261, 262), a pair of fourth inductors (271, 272), and a fifth inductor (291), and the pair of third inductors (211, 212) is respectively connected to one of the pair of first capacitors (251, 252) in series after respectively passing through one of the pair of second capacitors (221, 222) connected in parallel, is respectively connected to one of the pair of ground inductors (261, 262) in parallel, and at the same time is respectively connected to one of the pair of fourth inductors (271, 272) in series, and is combined to be connected to an output end through the serially connected fifth inductor (291). |
