APPARATUS AND METHOD FOR INTERFACING BETWEEN CENTRAL PROCESSING UNIT AND MAIN MEMORY UNIT

摘要

Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

主权项

1. An apparatus for interfacing between a central processing unit (CPU) and a main memory unit, the apparatus comprising:
a master optical connection protocol engine configured to convert operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter configured to convert the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter configured to convert the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine configured to convert the serial signals converted by the second E/O converter into operation control signals; and a memory controller configured to access to the main memory unit based on the operation control signals converted by the slave optical connection protocol engine.