发明名称 配線データの生成装置、生成方法、そのプログラム、および描画装置
摘要 <p>It is an object to generate wiring data while controlling generation of omission of wiring and shortening process time. In order to achieve this object, a device for generating wiring data includes: an error acquiring part that acquires a configuration error of the semiconductor chip relative to a certain reference position and a certain reference angle on the substrate; an area information acquiring part that acquires enclosing area information indicating an enclosing area enclosing the semiconductor chip on the substrate; and a wiring data generating part that generates enclosing area wiring data indicating an enclosing area wiring pattern based on a reference fan-out line established for a reference chip free from a configuration error and being a part of a reference wiring pattern free from faulty wiring. The enclosing area wiring pattern is a part of the connection wiring pattern and covers the enclosing area. The wiring data generating part generates the enclosing area wiring data such that the position and the angle of the reference fan-out line relative to the reference chip, and the position and the angle of a fan-out line for the semiconductor chip on the substrate relative to this semiconductor chip, agree with each other independently of the configuration error.</p>
申请公布号 JP5779145(B2) 申请公布日期 2015.09.16
申请号 JP20120145880 申请日期 2012.06.28
申请人 发明人
分类号 H01L21/02;G03F7/20;H01L21/027;H01L21/60 主分类号 H01L21/02
代理机构 代理人
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