| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce the workload occurring in the actual circuit design, when mounting a router or a switch on a communication device.SOLUTION: In a reception unit 1i, an input side elastic buffer 5j is provided for each interface standard #j, a parallel signal Rj and a serial clock signal Fj are inputted, the Rj is written in an internal buffer on the basis of the Fj, the Rj is read from the internal buffer on the basis of the Fj, and outputted to a MAC control logic core 2j. The MAC control logic core 2j distributes the Fj outputted from a SerDes 10 as an internal clock signal, and decodes the Rj outputted from the SerDes 10 on the basis of the internal clock signal, thus generating and outputting the packet data of the interface standard #j.</p> |
