发明名称 半導体集積回路及びその設計方法
摘要 <p><P>PROBLEM TO BE SOLVED: To determine the state of a tap controller at the time of logical simulation, even if there is no TRST as the external terminal of a semiconductor integrated circuit. <P>SOLUTION: A tap controller 2 has a reset terminal (terminal p4). A circuit 3 receives a state control signal for controlling the state transition in the tap controller 2, and a clock signal, and then determines the state of the tap controller 2 by supplying a reset signal to the reset terminal p4 according to the state control signal and the clock signal. <P>COPYRIGHT: (C)2013,JPO&INPIT</p>
申请公布号 JP5772326(B2) 申请公布日期 2015.09.02
申请号 JP20110157088 申请日期 2011.07.15
申请人 发明人
分类号 H01L21/822;G01R31/28;G06F17/50;H01L27/04 主分类号 H01L21/822
代理机构 代理人
主权项
地址