发明名称 Thin-film transistor and method for manufacturing the same
摘要 Disclosed herein is a thin film transistor. The thin film transistor is characterized in having a source interconnect layer and a drain interconnect layer. The source electrode and the drain electrode are respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer. The semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, but is not in contact with the source electrode and the drain electrode.
申请公布号 US9123691(B2) 申请公布日期 2015.09.01
申请号 US201213615640 申请日期 2012.09.14
申请人 E Ink Holdings Inc. 发明人 Wang Henry;Yeh Chia-Chun;Tsai Xue-Hung;Wang Chih-Hsuan;Shinn Ted-Hong
分类号 H01L29/417;H01L29/10;H01L29/786 主分类号 H01L29/417
代理机构 CKC & Partners Co., Ltd. 代理人 CKC & Partners Co., Ltd.
主权项 1. A thin film transistor, comprising: a substrate having a principal surface; a gate electrode disposed on the principal surface of the substrate; a gate insulating layer covering the gate electrode and the substrate; a source interconnect layer and a drain interconnect layer disposed on the gate insulating layer, wherein the source interconnect layer is spaced apart from the drain interconnect layer by a gap; a source electrode and a drain electrode respectively disposed above and in contact with the source interconnect layer and the drain interconnect layer; and a semiconductor layer disposed above the gate insulating layer at a position overlapped with the gate electrode, wherein the semiconductor layer is in contact with both the source interconnect layer and the drain interconnect layer, and filled in the gap between the source interconnect layer and the drain interconnect layer, wherein an edge of the source interconnect layer and an edge of the drain interconnect layer are interposed between the semiconductor layer and the gate insulating layer, wherein the semiconductor layer is not overlapped with the source electrode and the drain electrode when observed in a direction perpendicular to the principal surface of the substrate, and the source electrode and the drain electrode are spaced apart from the semiconductor layer by clearances through which portions of the source interconnect layer and the drain interconnect layer are exposed.
地址 Hsinchu TW