| 摘要 |
<p>A semiconductor device comprises a section signal generation part generating a section signal by delaying a displacement section signal including pulse generated during reading and writing operations with the delay amount set upon level combination of first and second test mode signals; and a decoder decoding an address at a point when the pulse of the section signal is generated, and generating a selectively enabled column selection signal for storing in a memory cell included in an internal circuit or outputting the same.</p> |
