发明名称 SEMICONDUCTOR DEVICE
摘要 A semiconductor device includes a semiconductor substrate on which plural gate electrodes are juxtaposed to each other, plural gate wirings formed on the semiconductor substrate, plural gate pads, a first pad, and a second pad. The adjacent gate electrodes define plural cells, and the plural cells include plural transistor cells. The plural gate electrodes are partitioned into plural types by the plural gate wirings. The plural transistor cells are partitioned into plural types according to a combination of the defined gate electrodes.
申请公布号 US2015221566(A1) 申请公布日期 2015.08.06
申请号 US201314432368 申请日期 2013.10.21
申请人 DENSO CORPORATION 发明人 Ookura Yasushi
分类号 H01L21/66;G01R31/26;H01L27/088 主分类号 H01L21/66
代理机构 代理人
主权项 1. A semiconductor device, comprising: a semiconductor substrate having a first surface and a second surface that is located opposite to the first surface in a thickness direction, and including a plurality of gate electrodes that is juxtaposed in a first direction orthogonal to the thickness direction, the adjacent gate electrodes defining a plurality of cells, and the plurality of cells including a plurality of transistor cells; a plurality of gate wirings formed on the first surface of the semiconductor substrate and electrically connected to the plurality of gate electrodes; a plurality of gate pads formed on the first surface of the semiconductor substrate and electrically connected to the plurality of gate electrodes through the plurality of gate wirings; a first pad formed on the first surface of the semiconductor substrate and common to the plurality of transistor cells; and a second pad formed on one of the first surface and the second surface of the semiconductor substrate and common to the plurality of transistor cells, wherein the plurality of gate wirings electrically partitioned from each other is connected to the respective gate pads, the plurality of gate electrodes is electrically partitioned into a plurality of types according to the plurality of gate wirings, and the plurality of transistor cells is partitioned into a plurality of types by a combination of the defined gate electrodes.
地址 Kariya-city, Aichi JP