发明名称 Relaxation oscillator
摘要 In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
申请公布号 US9099994(B2) 申请公布日期 2015.08.04
申请号 US201213721885 申请日期 2012.12.20
申请人 Silicon Laboratories Inc. 发明人 Thomsen Axel;Konecny Pavel;Wang Xiaodong
分类号 H03K3/011;H03K3/0231 主分类号 H03K3/011
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. An apparatus comprising: a first capacitor to pre-charge to a first voltage exceeding a first reference voltage by a first delay compensation voltage during a first portion of a clock period and thereafter to charge to a second voltage exceeding a second reference voltage by a second delay compensation voltage during a second portion of the clock period; a second capacitor to charge to the second voltage during the first portion of the clock period and to pre-charge to the first voltage during the second portion of the clock period; a first comparator coupled to the first capacitor to compare a first voltage of the first capacitor to the first reference voltage during the first clock period portion and to compare the first capacitor voltage to the second reference voltage during the second clock period portion and to provide a first comparison output to a timing logic circuit; and a second comparator coupled to the second capacitor to compare a voltage of the second capacitor to the second reference voltage during the first clock period portion and to compare the second capacitor voltage to the first reference voltage during the second clock period portion and to provide a second comparison output to the timing logic circuit; wherein the timing logic circuit receives the first comparison output and the second comparison output and generates a clock signal based thereon.
地址 Austin TX US