SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS

摘要

A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

主权项

1. An integrated circuit comprising:
A. functional logic; B. test circuitry having a test clock in lead, a test mode select in lead, a test data in lead, and a test data out lead, the test circuitry including a test access port controller, which includes a state machine, that is connected to the test clock in lead and the test mode select in lead and that has control outputs, an instruction register having an input connected to the test data in lead, an output coupled to the test data out lead and a control input connected to the control outputs of the controller, and a data register having a serial input connected to the test data in lead, a serial output coupled to the test data out lead, and inputs and outputs coupled to the functional logic; and C. adapter circuitry including: i. a first set of leads including: a. a clock input lead, b. a mode input and output lead, c. a test in data lead, and d. a test out data lead, ii. a second set of leads having:
a. a test clock out lead carrying a test clock signal coupled to the test clock in lead of the test circuitryb. a test mode select out lead carrying a test mode select signal coupled to the test mode select in lead of the test circuitry,c. a test in data output lead carrying a test in data signal coupled to the test data in lead of the test circuitry, andd. a test out data input lead carrying a test out data signal coupled to the test data out lead of the test circuitry; and iii. a transport control register coupled to the first set of leads, the scan control register having bit locations for:
a. background data transfer format,b. background data transfer enable,c. custom data transfer enable, andd. background data transfer selection.