发明名称 Semiconductor device
摘要 There is a need to cause a delay to occur less frequently than the related art during processing of an input signal in need of relatively fast processing. In a semiconductor device, a conversion portion includes first channels and second channels and A/D converts a signal input to a selected channel. A signal input to the first channel requires faster processing than a signal input to the second channel. The conversion portion receives a scan conversion instruction from a central processing unit, sequentially selects the input channels in a specified selection order, and successively performs A/D conversion. In this case, the conversion portion notifies a peripheral circuit of completion of A/D conversion after completion of A/D conversion on signals input to the first channels and before completion of A/D conversion on input signals input to all input channels.
申请公布号 US9094037(B2) 申请公布日期 2015.07.28
申请号 US201113331923 申请日期 2011.12.20
申请人 Renesas Electronics Corporation 发明人 Harada Daijiro;Utsumi Takashi
分类号 G06F3/00;H03M1/12 主分类号 G06F3/00
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A semiconductor device comprising: a central processing unit; a plurality of peripheral circuits including first and second peripheral circuits; and a conversion portion that has a plurality of input channels including one or more first channels and one or more second channels, a channel selection portion for selecting one of the input channels, and analog-to-digital (A/D) converter for converting a signal input from a selected input channel and outputting a selection signal to the channel selection portion and a completion signal, wherein signal processing in the first peripheral circuit uses an A/D conversion result on a signal input from the one or more first channels, wherein signal processing in the second peripheral circuit uses an A/D conversion result on a signal input from the one or more second channels, wherein the conversion portion receives a scan conversion instruction from the central processing unit, sequentially selects a respective one of the input channels in accordance with a selection signal from the channel selection portion based on a specified selection order, and successively performs A/D conversion, and wherein when the conversion portion performs a scan conversion in response to the scan conversion instruction, the first peripheral circuit receives a conversion result of the one or more first channels in response to the selection signal identified completion of A/D conversion and the second peripheral circuit receives a conversion result of the one or more second channels in response to the selection signal identified completion of A/D conversion for all input channels.
地址 Kanagawa JP