Integrated circuits and methods for operating integrated circuits with non-volatile memory

摘要

Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

主权项

1. An integrated circuit comprising:
a semiconductor substrate doped with a first conductivity-determining impurity and having formed therein:
a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity;a second well, formed within the first well, and doped with the first conductivity-determining impurity; anda third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity; a floating gate structure formed over the semiconductor substrate and comprising:
a first gate element disposed over the second well and being separated from the second well with a dielectric layer;a second gate element disposed over the third well and being separated from the third well with the dielectric layer; anda conductive connector that electrically connects the first and second gate elements; source and drain regions disposed in the second well and doped with the second conductivity-determining impurity, the source and drains regions having conductive contacts formed thereto, wherein the second well, the first gate element, the source and drain regions, and the dielectric layer form a transistor structure; a first terminal formed of electrical contacts to the first and second wells; and a second terminal formed of electrical contacts to the third well.