Information processor

摘要

To an existing instruction set, newly added are a condition code conversion instruction for converting a first condition code (N, Z, OV, C) to a second condition code (V, S) based on a reference condition code COND, a second conditional instruction having a reference flag SF, and an instruction of operation between two selected second condition codes. A VLIW processor comprises a second condition code register file 163, a condition code conversion circuit 12A, and a logic operation circuit 12E for performing a non-Boolean logic operation between two selected second condition codes.