发明名称 |
Minimum-spacing circuit design and layout for PICA |
摘要 |
PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology. |
申请公布号 |
US9081049(B2) |
申请公布日期 |
2015.07.14 |
申请号 |
US201314012668 |
申请日期 |
2013.08.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
Ainspan Herschel A.;Kim Seongwon;Stellari Franco;Weger Alan J. |
分类号 |
H03K19/00;G01R31/26;H03K19/094;H03K19/14 |
主分类号 |
H03K19/00 |
代理机构 |
Tutunjian & Bitetto, P.C. |
代理人 |
Tutunjian & Bitetto, P.C. ;Dougherty Anne V. |
主权项 |
1. A circuit, comprising:
a first semiconductor device and a second semiconductor device which emit light during operation, laid out such that light-emitting regions of the respective semiconductor devices are side-by-side with a gap between the respective light-emitting regions including a target resolution size. |
地址 |
Armonk NY US |