Method and apparatus for optimizing access to control registers in an emulation chip

摘要

The present patent document relates to a method and apparatus for optimizing access to control registers in an emulation chip. Control messages include in one half of the message a write-mask bits for the corresponding control bits in the other half of the word. A single message from the host workstation can be used to update several bits of the register using a single message, rather than reading, modifying, then writing back each bit individually. Only the bits desired to be updated are written, while the masked bits are not affected. Various configurations of the mask bits and control bits are possible, and block transfers can be used to update bits across a series of registers. The disclosed method and apparatus can reduce overhead and latency on communication channels to the host workstation by significantly reducing the number of individual transfer across the channel.

主权项

1. A method of updating registers of a plurality of hardware resources in an emulation system comprising:
receiving a message at a communication interface, the message addressed to a register set of a hardware resource of the emulation system and carrying a word that includes a plurality of mask bits and a plurality of new control bits; reading a plurality of old control bits from a plurality of control registers of the register set; operating on the plurality of old control bits with the plurality of mask bits and the plurality of new control bits to generate a plurality of updated control bits; and writing the plurality of updated control bits to the plurality of control registers of the register set, wherein the new control bits comprise one or more configuration bits and one or more trigger bits, wherein each configuration bit of the one or more configuration bits is written to the plurality of control registers prior to when any trigger bit of the one or more trigger bits are written to the plurality of control registers during writing the plurality of updated control bits to the plurality of control registers of the register set.