| 摘要 |
Two selection signals (CLK<1> and CLK<2>) that reach significant levels sequentially are inputted to this signal multiplexer (1), as are two input signals (IN<1> and IN<2>). When the mth selection signal (CLK<m>) is at a significant level, the signal multiplexer (1) outputs a signal (OUT) corresponding to the mth input signal (IN<m>) via an output terminal (14). The signal multiplexer (1) is provided with a resistance unit (20) and two drive units (301 and 302). Each drive unit (30m) comprises a driving switch (31m), a selecting switch (32m), and a potential-stabilizing switch (33m). In each drive unit (30m), when that selecting switch (32m) is closed, that potential-stabilizing switch (33m) is open, and vice versa. |
