IQ Gain Imbalance Correction For Receivers Employing Sigma-Delta Analog To Digital Conversion

摘要

An apparatus for improving a gain imbalance between an in-phase and quadrature component recovered by a receiver is provided. The apparatus includes a first transition counter configured to count a number of bit transitions in a first sequence of one-bit values provided by a first sigma-delta modulator based on the in-phase component, and a second transition counter configured to count a number of bit transitions in a second sequence of one-bit values provided by a second sigma-delta modulator based on the quadrature component. The apparatus further includes a gain monitor configured to: (1) determine a first and second power level, proportional to a power of the in-phase and quadrature components respectively, using the number of bit transitions in the first and second sequences, and (2) adjust a gain of one of the in-phase and quadrature components based on a ratio between the first and second power levels.

主权项

1. A receiver comprising:
a first sigma-delta modulator configured to convert an in-phase component of a received signal into a first discrete time signal comprising a first sequence of one-bit values; a second sigma-delta modulator configured to convert a quadrature component of the received signal into a second discrete time signal comprising, a second sequence of one-bit values; and a gain monitor configured to adjust a gain of the receiver based on a ratio between a first power level, determined based on a number of bit transitions in the first sequence of one-bit values, and a second power level, determined based on a number of bit transitions in the second sequence of one-bit values.