Isolating failing latches using a logic built-in self-test

摘要

A mechanism is provided for identifying a failing latch within an integrated circuit device. A test sequence is initiated on a set of scan chains associated with an identified failing multiple input signature register. For each test portion in a set of test portions in the test sequence, a comparison is performed between an output of the multiple input signature register and a corresponding value in a set of expected values. Responsive to determining a match, a value of a counter is incremented. Responsive to a failure to match, incrementing of the counter is stopped, and the value of the counter providing an indication of the failing latch in the integrated circuit device is read out.

主权项

1. A method, in an integrated circuit device, for identifying a failing latch within the integrated circuit device, comprising:
loading a set of expected values for a set of scan chains associated with a multiple input signature register into a data structure; initializing a counter to an initial value; initiating a test sequence on the set of scan chains associated with the multiple input signature register, wherein the test sequence comprises a set of test portions; and for each of the set of test portions:
comparing an output of the multiple input signature register to a corresponding value in the set of expected values;responsive to determining a match between the output of the multiple input signature register to the corresponding value in the set of expected values, incrementing the counter; andresponsive to determining that the output of the multiple input signature register does not match the corresponding value in the set of expected values:
stopping the increment of the counter, andreading out the value of the counter to identify the failing latch in the integrated circuit device.