Retirement serialisation of status register access operations

摘要

A processor 2 for performing out-of-order execution of a stream of program instructions includes a special register access pipeline for performing status access instructions accessing a status register 20. In order to serialise these status access instructions relative to other instructions within the system access timing control circuitry 32 permits dispatch of other instructions to proceed but controls the commit queue and the result queue such that no program instructions in program order succeeding the status access instruction are permitted to complete until after a trigger state has been detected in which all program instructions preceding in program order the status access instruction have been performed and made any updates to the architectural state. This is followed by the performance of the status access instruction itself.

主权项

1. Apparatus for executing a stream of program instructions, said apparatus comprising:
a plurality of processing pipelines including a special register pipeline configured to respond to a status access instruction to perform a status register access operation to a status register configured to store at least one state variable; dispatch queue circuitry configured to store a dispatch queue of undispatched program instructions awaiting dispatch to one of said plurality of pipelines and to dispatch said status access instruction to said special register pipeline; commit queue circuitry configured to store a commit queue of uncommitted program instructions awaiting a determination to be permitted to complete processing; result queue circuitry configured to store a result queue of unretired program instructions yet to update architectural state variables; and access timing control circuitry coupled to said special register pipeline, said commit queue circuitry and said result queue circuitry, said access timing control circuitry being configured such that, when said status access instruction is issued to said special register pipeline and while program instructions continue to be dispatched from said dispatch queue, said access timing control circuitry: (i) controls said commit queue circuitry such that no program instruction succeeding in program order said status access instruction within said stream of program instructions is permitted to complete processing; (ii) detects from said result queue circuitry a trigger state when all program instructions preceding in program order said status access instruction within said stream of program instructions have performed any updates to architectural state variables of said apparatus; and (iii) upon detection of said trigger state, triggers said special register pipeline to perform said status register access operation, comprising special register issue queue circuitry, each entry within said special register issue queue circuitry including an issue policy field for storing an issue policy value specifying one of a plurality of issue politics to be applied to issuing of a program instruction corresponding to said entry to said special register pipeline.