| 摘要 |
<p>A semiconductor device includes a memory bank, a row decoder, and a cross domain circuit. The memory bank includes a dummy block and a plurality of sub blocks. The row decoder is individually allocated to the dummy block and a plurality of sub blocks, including a plurality of block selecting units which select the dummy block and a plurality of sub blocks based on a row address signal, a lag bank selecting signal, and a dummy lag bank selecting signal. The cross domain circuit lags a bank selecting signal, generating the lag bank selecting signal and the dummy lag bank selecting signal.</p> |
