发明名称 Banking of reliability metrics
摘要 In one embodiment, a processor includes at least one functional block and banking logic. The banking logic may be to determine an average reliability metric associated with the at least one functional block. The banking logic may also be to, if the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, where the reduced reliability mode is associated with a reduction in the average reliability metric. Other embodiments are described and claimed.
申请公布号 US9043659(B2) 申请公布日期 2015.05.26
申请号 US201213729400 申请日期 2012.12.28
申请人 Intel Corporation 发明人 Herrero Abellanas Enric;Vera Xavier;Carretero Casado Javier;Ramirez Tanausu;Axelos Nicholas;Sanchez Daniel
分类号 G06F11/00 主分类号 G06F11/00
代理机构 Trop, Pruner & Hu, P.C. 代理人 Trop, Pruner & Hu, P.C.
主权项 1. A processor comprising: at least one functional block; and banking logic to: determine a plurality of current reliability metric values associated with the at least one functional block, each of the plurality of current reliability metric values corresponding to a unique point in time;store the plurality of current reliability metric values in a storage of the processor;average the stored plurality of current reliability metric values to obtain an average reliability metric associated with the at least one functional block; andif the average reliability metric exceeds a required level, implement a reduced reliability mode in the at least one functional block, wherein the reduced reliability mode is associated with a reduction in the average reliability metric.
地址 Santa Clara CA US