REDUCED RESISTANCE FINFET DEVICE WITH LATE SPACER SELF ALIGNED CONTACT

摘要

Embodiments include a method of fabricating a reduced resistance finFET device comprising providing a fin in a semiconductor substrate. A dummy gate is formed over a portion of the fin such that the dummy gate does not initiate selective epitaxy. A source/drain region is formed on the fin such that the source/drain region directly contacts the dummy gate. The dummy gate is replaced with a replacement metal gate structure that directly contacts the source/drain region. A portion of the fin that includes a portion of the source/drain region is replaced with a contact material.

主权项

1. A finFET device, the device comprising:
a fin formed in a semiconductor substrate; a source/drain region formed over a portion of the fin; a gate structure formed over at least a portion of the fin, wherein the gate structure directly contacts a portion of the formed source/drain region; an insulating layer over at least a portion of the fin, the source/drain region and the gate structure; and an opening in at least a portion of the insulating layer, at least a portion of the source/drain region, and at least a portion of the fin, wherein the opening is adjacent the gate structure.