| 摘要 |
<p>In one embodiment, a method is provided for generating dataflow-driven simulation code of a circuit design described with a combination of first and second HDLs. The circuit description is elaborated and a simulation dataflow graph of the circuit description is generated. Simulation code, configured to model execution of the design in a data-driven manner according to the simulation dataflow graph, is generated from the dataflow graph using a first HDL signal representation having a format compatible with the first HDL and a second HDL signal representation having a format compatible with the second HDL. For each instantiated module of the circuit description at a cross language boundary in the simulation dataflow graph, ports of the instantiated module are mapped to the first HDL signal representation and mapped to the second HDL signal representation.</p> |
