发明名称 トランジスタ装置、集積回路及び製造方法
摘要 Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
申请公布号 JP5714722(B2) 申请公布日期 2015.05.07
申请号 JP20130546324 申请日期 2011.12.20
申请人 インテル コーポレイション 发明人 グラス,グレン エー.;マーシー,アナンド エス.
分类号 H01L21/336;B82Y30/00;B82Y40/00;H01L21/28;H01L29/06;H01L29/41;H01L29/78;H01L29/786 主分类号 H01L21/336
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