| 发明名称 |
Techniques for providing clock signals in an integrated circuit |
| 摘要 |
An integrated circuit includes a first vertical clock bus and a first interface circuit coupled to provide first global clock signals to the first vertical clock bus. The first interface circuit is coupled to a first external terminal of the integrated circuit. The integrated circuit also includes a second vertical clock bus and a second interface circuit coupled to provide second global clock signals to the second vertical clock bus. The second interface circuit is coupled to a second external terminal of the integrated circuit. A third horizontal clock bus is coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit. |
| 申请公布号 |
US9024673(B1) |
申请公布日期 |
2015.05.05 |
| 申请号 |
US201314075869 |
申请日期 |
2013.11.08 |
| 申请人 |
Altera Corporation |
发明人 |
Venkata Ramanand;Fung Ryan;Zaveri Ketan H. |
| 分类号 |
G06F1/04;G06F1/10 |
主分类号 |
G06F1/04 |
| 代理机构 |
|
代理人 |
Cahill Steven J. |
| 主权项 |
1. An integrated circuit comprising:
a first vertical clock bus; a first interface circuit coupled to provide first global clock signals to the first vertical clock bus, wherein the first interface circuit is coupled to a first external terminal of the integrated circuit; a second vertical clock bus; a second interface circuit coupled to provide second global clock signals to the second vertical clock bus, wherein the second interface circuit is coupled to a second external terminal of the integrated circuit; and a first horizontal clock bus coupled to provide the first and the second global clock signals from the first and the second vertical clock buses to a center region of the integrated circuit. |
| 地址 |
San Jose CA US |
