| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce variation in an input logical threshold of an input circuit, in a usage environment of a semiconductor device.SOLUTION: A semiconductor device includes: an NMOS ring oscillator 35 generating a first counter clock signal CCLK1; a PMOS ring oscillator 36 generating a second counter clock signal CCLK2; a counter circuit 38 counting up a count value according to the first counter clock signal CCLK1, counting down the count value according to the second counter clock signal CCLK2, and generating an adjustment signal Count<2:0> on the basis of the count value; and an input circuit 40 configured to adjust an input logical threshold according to the adjustment signal Count<2:0>.</p> |
