发明名称 |
DIGITAL PHASE LOCKED LOOP DEVICE AND METHOD IN WIRELESS COMMUNICATION SYSTEM |
摘要 |
A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval. |
申请公布号 |
EP2608413(A4) |
申请公布日期 |
2015.04.22 |
申请号 |
EP20110818426 |
申请日期 |
2011.08.19 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD;KONKUK UNIVERSITY INDUSTRIAL COOPERATION CORP. |
发明人 |
LEE, KANG-YOON;PU, YOUNG-GUN;PARK, AN-SOO;PARK, JOON-SUNG;LEE, JAE-SUP |
分类号 |
H03L7/089;H03L7/091 |
主分类号 |
H03L7/089 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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