Static random access memory devices having read and write assist circuits therein that improve read and write reliability

摘要

Integrated circuit memory devices include a memory cell configured to receive a power supply signal and a write assist circuit. The write assist circuit is configured to improve write margins by reducing a magnitude of the power supply signal supplied to the memory cell from a first voltage level to a lower second voltage level during an operation to write data into the memory cell. The memory device further includes at least one bit line electrically coupled to the memory cell and a read assist circuit. The read assist circuit may be configured to improve read reliability by partially discharging the at least one bit line from an already precharged voltage level to a lower third voltage level in preparation to read data from the memory cell.

主权项

1. An integrated circuit memory device, comprising:
a memory cell configured to receive a power supply signal on a power supply signal line; a write assist circuit electrically coupled to the power supply signal line, said write assist circuit configured to reduce a magnitude of the power supply signal supplied to said memory cell from a first voltage level to a lower second voltage level during an operation to write data into said memory cell; and a read assist circuit electrically coupled to said memory cell by at least one bit line, said read assist circuit configured to partially discharge the at least one bit line from a precharged voltage level established during a precharge time interval to a lower third voltage level in preparation to read data from said memory cell during a read time interval.