发明名称 Bumped semiconductor wafer or die level electrical interconnect
摘要 A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station.
申请公布号 US8988093(B2) 申请公布日期 2015.03.24
申请号 US201213413032 申请日期 2012.03.06
申请人 Hsio Technologies, LLC 发明人 Rathburn James
分类号 G01R1/067;G01R31/28 主分类号 G01R1/067
代理机构 Stoel Rives LLP 代理人 Stoel Rives LLP
主权项 1. A probe assembly to act as a temporary interconnect between terminals on an IC device and a test station, the probe assembly comprising: a substrate comprising a dielectric material; a plurality of conductive stud bumps arranged on a first surface of the substrate in a configuration corresponding to the terminal on the IC device, the stud bumps comprising a shape adapted to temporarily couple with the terminals on the IC device; a plurality of conductive traces located on the substrate electrically coupled with the test station and proximal ends of one or more of the stud bumps; and a compliant layer supporting the proximal ends of the stud bumps, the compliant layer adapted to elastically bias the stud bumps toward the terminals on the circuit member and to compensate for non-planarity of the terminal.
地址 Maple Grove MN US