Circuit and Method for Monolithic Stacked Integrated Circuit Testing

摘要

A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis.

主权项

1. A monolithic stacked integrated circuit (IC) comprising a known-good-layer (KGL) test circuit and a scan segment in a first layer of the IC, the KGL test circuit comprising:
a first test input, coupled to an input of the scan segment, to receive a first scan shift data; a first multiplexer, the first multiplexer having two data inputs, a selection input, and a data output wherein one data input of the first multiplexer is coupled to the first test input and another data input of the first multiplexer is coupled to an output of the scan segment; a first test output, coupled to the data output of the first multiplexer, to send a second scan shift data to a second layer; a second test input, to receive a third scan shift data from the second layer; a second multiplexer, the second multiplexer having two data inputs, a selection input, and a data output wherein one data input of the second multiplexer is coupled to the second test input and another data input of the second multiplexer is coupled to the data output of the first multiplexer; a second test output, coupled to the data output of the second multiplexer, to send a fourth scan shift data; a first control element, coupled to the selection input of the first multiplexer; and a second control element, coupled to the selection input of the second multiplexer.