DUAL-PORT NEGATIVE LEVEL SENSITIVE RESET DATA RETENTION LATCH

摘要

In an embodiment of the invention, a dual-port negative level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes low, CLKZ goes high, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLKZ, the retain control signal RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

主权项

1. A dual-port negative level sensitive reset data retention latch comprising:
a clocked inverter configured to receive a first data bit (D1), clock signal (CKT), clock signal (CLKZ), a reset control signal (REN) and retention mode control (RET) wherein (CKT), (CLKZ), (RET) and (REN) determine whether the data output (QN) from the clocked inverter is the binary compliment of data bit (D1) or an indeterminate value; a dual-port latch configured to receive the output (QN) of the clocked inverter, a second data bit (D2), the clock signal (CKT), the clock signal (CLKZ), the retain control signal (RET), a reset control signal (REN), a latch control signal (SS) and a latch control signal (SSN) wherein signals (CKT), (CLKZ), (RET), (REN), (SS) and (SSN) determine whether the output (QN) of the clocked inverter or the second data bit (D2) is latched in the dual-port latch.