Architecture for 3-D NAND memory

摘要

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

主权项

1. An apparatus, comprising:
a plurality of stacked arrays, including:
memory strings of a first array of memory cell strings coupled between a first source and a first data line;memory strings of a second array of memory cell strings coupled between a second source and a second data line; a shared data detector coupled to both the first data line and the second data line; and a first switch coupled between the first data line and the shared data detector and a second switch coupled between the second data line and the shared data detector, and a third switch coupled between the first data line and an inhibit voltage source and a fourth switch coupled between the second data line and the inhibit voltage source.