发明名称 |
AMPLIFIER CIRCUIT |
摘要 |
An amplifier circuit is configured in such a manner that the withstand voltage between the terminals of a FET 2 (withstand voltage B) is higher than the withstand voltage between the terminals of a FET 1 (withstand voltage A), and that the gate width of the FET 1 (Wg1) is narrower than the gate width of the FET 2 (Wg2). This makes it possible to increase the gain while maintaining high output power. The narrow gate width of the FET 1 (Wg1) connected to an input terminal 3 enables reducing the size of the cascode amplifier. |
申请公布号 |
US2015048887(A1) |
申请公布日期 |
2015.02.19 |
申请号 |
US201314387726 |
申请日期 |
2013.03.12 |
申请人 |
Nitta Naoko;Kato Katsuya;Mukai Kenji;Horiguchi Kenichi;Hieda Morishige;Mori Kazutomi;Yamamoto Kazuya |
发明人 |
Nitta Naoko;Kato Katsuya;Mukai Kenji;Horiguchi Kenichi;Hieda Morishige;Mori Kazutomi;Yamamoto Kazuya |
分类号 |
H03F1/02;H03F3/193;H03F3/21 |
主分类号 |
H03F1/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
Tokyo JP |