Memory system having high data transfer efficiency and host controller

摘要

According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor.

主权项

1. A host controller which is connected to a memory device through an interface, accesses a system memory, and is controlled by a CPU executing a host driver, wherein each of first, third, and fourth descriptors has an attribute field for identifying a type of the descriptors, and designating a processing method of the descriptors, the host controller comprising:
a register set which is configured to store a part of information in the third descriptor; a command controller which is configured to issue a command to the memory device according to the information stored in the register set; and a direct memory access (DMA) unit which is configured to load the first, third, and fourth descriptors into the host controller, and is configured to transfer data between the system memory and the memory device according to the first, third, and fourth descriptors, wherein the first descriptor includes a plurality of pointers with attributes, each of the pointers of the first descriptor indicates a leading region of the third descriptor, the third descriptor includes command issue information and attributes, the fourth descriptor includes a number of DMA execution information and attributes, and wherein the DMA unit is configured (1) to load the first descriptor, (2) to acquire the pointer from the loaded first descriptor, (3) to load the third descriptor and the fourth descriptor based on the acquired pointer, (4) to execute a data transfer between the system memory and the memory device, (5) to repeat the process of (2) to (4) until the attribute of the first descriptor indicates the end of descriptor, and (6) to generate an interrupt to the CPU when the data transfer is end or during a DMA data transfer, wherein the third descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks; and wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory.