| 主权项 |
1. A memory apparatus, comprising:
a semiconductor substrate; a plurality of memory cells, each including a switching element and a variable resistor connected in parallel, stacked on the semiconductor substrate; and a plurality of word lines connected to the plurality of memory cells by a one-to-one correspondence to control operations of the plurality of memory cells, wherein the plurality of memory cells are configured to be connected to each other in series, wherein the switching element includes a channel layer extending in a direction perpendicular to a surface of the semiconductor substrate, a plurality of gates extending in a direction parallel to the surface of the semiconductor substrate from one sidewall of the channel layer and arranged at intervals in the direction perpendicular to the surface of the semiconductor substrate, and source and drain interconnections each extending in the direction parallel to the surface of the semiconductor substrate from the other sidewall of the channel layer and arranged between adjacent gates, and wherein the variable resistor is interposed between the source and drain interconnections to be electrically coupled with the source and drain interconnections. |
