MEMORY DEVICE IMPLEMENTING REDUCED ECC OVERHEAD

摘要

A memory device using error correction code (ECC) implements a memory array parallel read-write method to reduce the storage overhead required for storing ECC check bits. The memory array parallel read-write method stores incoming address and data into serial-in parallel-out (SIPO) address registers and write data registers, respectively. The stored data are written to the memory cells in parallel when the SIPO registers are full. ECC check bits are generated for the block of parallel input data stored in the write data registers. During the read operation, a block of read out data corresponding to the read address are read from the memory cells in parallel and stored in read registers. ECC correction is performed on the block of read out data before the desired output data is selected for output.

主权项

1. A memory device, comprising:
a memory array comprising a first memory array area configured to store memory data and a second memory array area configured to store error correction code associated with the memory data; a data input circuit comprising a set of serial-in-parallel-out write data registers, the data input circuit being configured to receive serial input data in response to a write signal and a write address, the serial input data being shifted into the write data registers in response to a clock signal, the data input circuit configured to convert the serial input data stored in the write data registers into a set of parallel input data, the parallel input data being provided to the memory array to be written to the first memory array area; and an error correction code (ECC) generation circuit configured to receive the set of the parallel input data and to generate an ECC data word associated with the set of parallel input data, the ECC data word being stored in the second memory array area.