发明名称 |
A DIGITAL PHASE-LOCKED LOOP CLOCK SYSTEM |
摘要 |
A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitally-controlled oscillator (DCO) including a sigma-delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for storing the difference signal over time. The SDM may have a control input coupled to the buffer. The adder may have inputs coupled to the SDM and a source of an integer control word. The first frequency divider may have an input for receiving an external clock signal and a control input coupled to the adder, the DCO generating an output clock signal having an average frequency representing a frequency of the external clock signal divided by (N+F/M). |
申请公布号 |
EP2596584(A4) |
申请公布日期 |
2015.01.14 |
申请号 |
EP20110810037 |
申请日期 |
2011.06.15 |
申请人 |
ANALOG DEVICES, INC. |
发明人 |
ZHU, DAN;NELSON, REUBEN, PASCAL;RAITHATHA, TIMIR;PALMER, WYN;CAVEY, JOHN;ZHENG, ZIWEI |
分类号 |
H03L7/099;H03L7/14;H03L7/18 |
主分类号 |
H03L7/099 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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