Clock-delayed domino logic circuit and devices including the same

摘要

A clock-delayed domino logic circuit includes a precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal, an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal, a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals, and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal.

主权项

1. A clock-delayed domino logic circuit comprising:
precharge circuit configured to control connection between a first node and a dynamic node in response to a clock signal; an evaluation circuit configured to control connection between a second node and an evaluation node in response to the clock signal; a logic network connected between the dynamic node and the evaluation node, the logic network configured to determine a logic level of the dynamic node based on a plurality of input signals; and a phase control circuit configured to output a logic level of the evaluation node or a logic level of the first node according to a level of the clock signal, wherein the phase control circuit includes an inverter connected between the first node and the evaluation node, wherein the inverter is configured to invert the clock signal.